SPEC 001 · evidence ledger
Coprocessor, not a mythic die.
The E47 mathematics is closed. The 7 nm numbers are targets. This page keeps those layers from contaminating each other — the same rule as the Kartekeya construct: no evidence propagates automatically to the next layer.
Physical instantiation (H0)
- process
- 7 nm FinFET (target)
- dieArea
- 0.35 mm²
- power
- 0.55 mW
- throughput
- 800k ops/s
- latency
- 1.25 ns
- analogClock
- 10 GHz
- digitalClock
- 3 GHz
- dmaMask
- 47-bit validity mask
- payload
- 47 × 32 = 1,504 bits (E47 coordinates)
- ambient
- 125 × 32 = 4,000 bits
- arithmetic
- Q4.28 normalized Ķ = K/432
Bit-length independence is real at the algebraic layer: a 512-bit and a 4096-bit modulus occupy the same 125-dimensional carrier. Area, power, 10 GHz analog, and 1.25 ns latency have no foundry report, STA, or GDS in the reviewed corpus.
Interface correction
- Rank 47 ≠ 47-bit bus.
- E47 state: 47 coordinates × 32 bits = 1,504 bits.
- Ambient carrier: 125 × 32 = 4,000 bits.
- Optional 47-bit field: validity / sector mask, not the payload.
- Q4.28 cannot hold unscaled K² (‖K²‖ = 186624). Use Ķ = K/432, α = 32/17.
- DSP48 names belong to AMD FPGA prototypes, not 7 nm standard cells.
Datapath options
Sparse product-basis
C has 605 nonzeros, K 1,139, K² 1,735 of 15,625.
CG-domain diagonal
U† x, scale by 1 − ε κ², U x. This lab uses this exact action.
Iterative normalized K²
x ← x − (32/17) Ķ² x. Streaming residual stop.
What is proven
| Claim | Status | Class |
|---|---|---|
| dim E₄₇ = 47 | Exact finite-dimensional identity | E0 |
| P₄₇ idempotence on Casimir spectrum | Polynomial interpolant verified | E0 |
| K² spectral gap 11664 … 186624 | Exact sector squares | E0 |
| ε* = 1/99144, ρ* = 15/17 | Minimax Richardson optimum | E0 |
| 7-qubit minimum embedding | 2⁶ < 125 ≤ 2⁷ | E0 |
| M₂ ⊕ M₅ noiseless multiplicity | Collective SU(2) algebra only | E0 |
| Discrete contraction Γ_εⁿ → P₄₇ | Live engine in this lab | E1 |
| Q4.28 noise floor ~ 6.55×10⁻⁸ | Monograph table reproduced in spirit | E1 |
| Correct synthesizable E47 RTL | Reference architecture, not closed | H0 |
| 0.35 mm² / 0.55 mW / 1.25 ns | SPEC 001 target, unverified silicon | H0 |
| 10 GHz phonon lock | Physical hypothesis | S0 |
| 13-pillar cryptographic security | Scheme / reduction pending | S0 |